Minimizing power consumption of electronic devices has long been a desirable goal within the electronics industry. Non-volatile memory devices minimize power consumption by being able to retain stored information when they don't receive power. Magnetoresistive random-access memory (MRAM) devices are one type of non-volatile memory device that enables long-term persistent storage while minimizing power consumption. MRAMs incorporate magnetic storage structures (e.g., Magnetic Tunnel Junctions (MTJ)) with Complementary Metal-Oxide Semiconductor (CMOS) transistors to form addressable read/write storage cells that may be used to store information within an electronic device.
The MTJs enable information to be stored using a magnetic properties of material rather than the materials capacitance properties. An MTJ typically comprises a tunneling barrier layer sandwiched between two ferromagnetic electrodes or metal layers. Accordingly, the MTJ may include conductive metallic layers to generate the magnetic state rather than dielectric layers that have been used in non-MRAM memory devices.
Manufacturing a MTJ using existing CMOS processing techniques has been challenging. In particular, etching multiple layers of different metals has been difficult to control and maintain MTJ performance. For example, etching residue that may be unintentionally deposited across multiple layers of the MTJ and may lead to electrical shorting across the MTJ. Further, etching non-uniformity across the microelectronic substrate may also introduce shorting defects by removing too much of a MTJ layer. Multi-step etching of the multiple metal layers may also introduce unintended sidewall modifications that may degrade MTJ storage capability. In fact, the complex multi-layer stacks of difficult to etch metals has limited the commercial proliferation of MRAM devices within the electronics industry. Accordingly, any MRAM manufacturing techniques that reduce the amount of metal etch process steps may be desirable.